The trend in integrated circuit design and fabrication is to shrink the size of individual devices to accommodate a greater number of devices on a substrate of a given size. As this trend continues, it becomes difficult to achieve the small feature sizes and the alignment between features which are necessary to fabricate highly reliable and high yielding devices. This problem is especially acute as the complexity of the device types used to implement a circuit function increases. The increasingly complex device types require an increase in the number of process steps used to fabricate the device and each of these process steps must be carefully and precisely interrelated. A single channel MOS device can be fabricated using only a few masking operations. The number of masking operations is increased considerably in fabricating CMOS structures. As the device structure becomes more complex and requires, for example, lightly doped drains (LDD), threshold adjust implants, and the like, more and more masking steps are required. When MOS is combined with bipolar to form a BiMOS or even BiCMOS structure, the number of processing steps increases even more. With these very complex structures it becomes even more important that critical device regions be self aligned and as the devices become smaller, that these critical regions be defined by other than conventional optical lithography. In the above referenced application, Ser. No. 309,589, a process is disclosed for the fabrication of an inverse T lightly doped drain (ITLDD) MOS structures that is highly manufacturable. A need existed, however, for a process for making small geometry bipolar transistors, and especially for the integration of such bipolar transistors with MOS transistors.
It is therefore an object of this invention to provide an improved process for fabricating a bipolar transistor.
It is another object of this invention to provide an improved process for fabricating bipolar and MOS transistors integrated in a BiMOS process.